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<p>This typedef contains configuration information for PLL type and its reference clock.  
 <a href="struct_x_hdmiphy1___channel.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ab40f4cd71a6a17e5fadfb0e51c96f310"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#ab40f4cd71a6a17e5fadfb0e51c96f310">LineRateHz</a></td></tr>
<tr class="memdesc:ab40f4cd71a6a17e5fadfb0e51c96f310"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">     The line rate for the
</pre><p> channel.  <a href="#ab40f4cd71a6a17e5fadfb0e51c96f310">More...</a><br/></td></tr>
<tr class="separator:ab40f4cd71a6a17e5fadfb0e51c96f310"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab051d1c6482506f1b3469f4f7310be01"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#ab051d1c6482506f1b3469f4f7310be01">RxDataWidth</a></td></tr>
<tr class="memdesc:ab051d1c6482506f1b3469f4f7310be01"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bits.  <a href="#ab051d1c6482506f1b3469f4f7310be01">More...</a><br/></td></tr>
<tr class="separator:ab051d1c6482506f1b3469f4f7310be01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abdf0d23bac376e9bab185c7625cc74e3"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#abdf0d23bac376e9bab185c7625cc74e3">RxIntDataWidth</a></td></tr>
<tr class="memdesc:abdf0d23bac376e9bab185c7625cc74e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bytes.  <a href="#abdf0d23bac376e9bab185c7625cc74e3">More...</a><br/></td></tr>
<tr class="separator:abdf0d23bac376e9bab185c7625cc74e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa25962f290f288e283801dd1b753bf2d"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#aa25962f290f288e283801dd1b753bf2d">TxDataWidth</a></td></tr>
<tr class="memdesc:aa25962f290f288e283801dd1b753bf2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bits.  <a href="#aa25962f290f288e283801dd1b753bf2d">More...</a><br/></td></tr>
<tr class="separator:aa25962f290f288e283801dd1b753bf2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a372c3ce24268dbda097c8413b1954a2a"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a372c3ce24268dbda097c8413b1954a2a">TxIntDataWidth</a></td></tr>
<tr class="memdesc:a372c3ce24268dbda097c8413b1954a2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">In bytes.  <a href="#a372c3ce24268dbda097c8413b1954a2a">More...</a><br/></td></tr>
<tr class="separator:a372c3ce24268dbda097c8413b1954a2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad2984727befa769d94409d039f2b9ff4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_hdmiphy1___pll_param.html">XHdmiphy1_PllParam</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#ad2984727befa769d94409d039f2b9ff4">CpllParams</a></td></tr>
<tr class="memdesc:ad2984727befa769d94409d039f2b9ff4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parameters for a CPLL.  <a href="#ad2984727befa769d94409d039f2b9ff4">More...</a><br/></td></tr>
<tr class="separator:ad2984727befa769d94409d039f2b9ff4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4f48b4acc5459494a985eb01d5ab6a62"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a4f48b4acc5459494a985eb01d5ab6a62">CpllRefClkSel</a></td></tr>
<tr class="memdesc:a4f48b4acc5459494a985eb01d5ab6a62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for the reference clock of the CPLL.  <a href="#a4f48b4acc5459494a985eb01d5ab6a62">More...</a><br/></td></tr>
<tr class="separator:a4f48b4acc5459494a985eb01d5ab6a62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a67bd659e6e97f698cdca013741601d2a"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a67bd659e6e97f698cdca013741601d2a">RxOutDiv</a></td></tr>
<tr class="memdesc:a67bd659e6e97f698cdca013741601d2a"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">     Output clock divider D for
</pre><p> the RX datapath.  <a href="#a67bd659e6e97f698cdca013741601d2a">More...</a><br/></td></tr>
<tr class="separator:a67bd659e6e97f698cdca013741601d2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6791024e367774619bbfeaedb022b6c1"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a6791024e367774619bbfeaedb022b6c1">TxOutDiv</a></td></tr>
<tr class="memdesc:a6791024e367774619bbfeaedb022b6c1"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">     Output clock divider D for
</pre><p> the TX datapath.  <a href="#a6791024e367774619bbfeaedb022b6c1">More...</a><br/></td></tr>
<tr class="separator:a6791024e367774619bbfeaedb022b6c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a42ccb139aa8c5a38d1b1446f57b9cb5c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga19e4c793abee3457123797eca4f61cd0">XHdmiphy1_GtState</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a42ccb139aa8c5a38d1b1446f57b9cb5c">RxState</a></td></tr>
<tr class="memdesc:a42ccb139aa8c5a38d1b1446f57b9cb5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current state of RX GT.  <a href="#a42ccb139aa8c5a38d1b1446f57b9cb5c">More...</a><br/></td></tr>
<tr class="separator:a42ccb139aa8c5a38d1b1446f57b9cb5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a779d9cc95fb049278ff2c9249022f800"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga19e4c793abee3457123797eca4f61cd0">XHdmiphy1_GtState</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a779d9cc95fb049278ff2c9249022f800">TxState</a></td></tr>
<tr class="memdesc:a779d9cc95fb049278ff2c9249022f800"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current state of TX GT.  <a href="#a779d9cc95fb049278ff2c9249022f800">More...</a><br/></td></tr>
<tr class="separator:a779d9cc95fb049278ff2c9249022f800"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af59b2132cb3e66b5f63a388feccac1d6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#af59b2132cb3e66b5f63a388feccac1d6">RxProtocol</a></td></tr>
<tr class="memdesc:af59b2132cb3e66b5f63a388feccac1d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The protocol which the RX path is used for.  <a href="#af59b2132cb3e66b5f63a388feccac1d6">More...</a><br/></td></tr>
<tr class="separator:af59b2132cb3e66b5f63a388feccac1d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a878cc570db337b4cf90acb555fcec00f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a878cc570db337b4cf90acb555fcec00f">TxProtocol</a></td></tr>
<tr class="memdesc:a878cc570db337b4cf90acb555fcec00f"><td class="mdescLeft">&#160;</td><td class="mdescRight">The protocol which the TX path is used for.  <a href="#a878cc570db337b4cf90acb555fcec00f">More...</a><br/></td></tr>
<tr class="separator:a878cc570db337b4cf90acb555fcec00f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f72133d80e15fefd3c0a396370d263e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a0f72133d80e15fefd3c0a396370d263e">RxDataRefClkSel</a></td></tr>
<tr class="memdesc:a0f72133d80e15fefd3c0a396370d263e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for the reference clock of the RX datapath.  <a href="#a0f72133d80e15fefd3c0a396370d263e">More...</a><br/></td></tr>
<tr class="separator:a0f72133d80e15fefd3c0a396370d263e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab47437f00b7226d61098050f2e222f2e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#ab47437f00b7226d61098050f2e222f2e">TxDataRefClkSel</a></td></tr>
<tr class="memdesc:ab47437f00b7226d61098050f2e222f2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for the reference clock of the TX datapath.  <a href="#ab47437f00b7226d61098050f2e222f2e">More...</a><br/></td></tr>
<tr class="separator:ab47437f00b7226d61098050f2e222f2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a285af4772a54f4c3f691dd1b7af66c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a7a285af4772a54f4c3f691dd1b7af66c">RxOutRefClkSel</a></td></tr>
<tr class="memdesc:a7a285af4772a54f4c3f691dd1b7af66c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for the reference clock of the RX output clock.  <a href="#a7a285af4772a54f4c3f691dd1b7af66c">More...</a><br/></td></tr>
<tr class="separator:a7a285af4772a54f4c3f691dd1b7af66c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afa0b12ee18fbb74ca031341a33f79bbb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#afa0b12ee18fbb74ca031341a33f79bbb">TxOutRefClkSel</a></td></tr>
<tr class="memdesc:afa0b12ee18fbb74ca031341a33f79bbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for the reference clock of the TX output clock.  <a href="#afa0b12ee18fbb74ca031341a33f79bbb">More...</a><br/></td></tr>
<tr class="separator:afa0b12ee18fbb74ca031341a33f79bbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59d9458edebc9248342e26fc0e17983b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga1b751875671500e5b0173be954368177">XHdmiphy1_OutClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a59d9458edebc9248342e26fc0e17983b">RxOutClkSel</a></td></tr>
<tr class="memdesc:a59d9458edebc9248342e26fc0e17983b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for which clock to use as the RX output clock.  <a href="#a59d9458edebc9248342e26fc0e17983b">More...</a><br/></td></tr>
<tr class="separator:a59d9458edebc9248342e26fc0e17983b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a193c1f3cd5fea5f09ce915f4d8281386"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__xhdmiphy1.html#ga1b751875671500e5b0173be954368177">XHdmiphy1_OutClkSelType</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a193c1f3cd5fea5f09ce915f4d8281386">TxOutClkSel</a></td></tr>
<tr class="memdesc:a193c1f3cd5fea5f09ce915f4d8281386"><td class="mdescLeft">&#160;</td><td class="mdescRight">Multiplexer selection for which clock to use as the TX output clock.  <a href="#a193c1f3cd5fea5f09ce915f4d8281386">More...</a><br/></td></tr>
<tr class="separator:a193c1f3cd5fea5f09ce915f4d8281386"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5d231c616ff8990611e9fa7a54fba87"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#ac5d231c616ff8990611e9fa7a54fba87">RxDelayBypass</a></td></tr>
<tr class="memdesc:ac5d231c616ff8990611e9fa7a54fba87"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">     Bypasses the delay
</pre><p> alignment block for the RX output clock.  <a href="#ac5d231c616ff8990611e9fa7a54fba87">More...</a><br/></td></tr>
<tr class="separator:ac5d231c616ff8990611e9fa7a54fba87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68edb50b3ab1a77bc3f86dee4893e30f"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_hdmiphy1___channel.html#a68edb50b3ab1a77bc3f86dee4893e30f">TxDelayBypass</a></td></tr>
<tr class="memdesc:a68edb50b3ab1a77bc3f86dee4893e30f"><td class="mdescLeft">&#160;</td><td class="mdescRight"><pre class="fragment">     Bypasses the delay
</pre><p> alignment block for the TX output clock.  <a href="#a68edb50b3ab1a77bc3f86dee4893e30f">More...</a><br/></td></tr>
<tr class="separator:a68edb50b3ab1a77bc3f86dee4893e30f"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains configuration information for PLL type and its reference clock. </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="ad2984727befa769d94409d039f2b9ff4"></a>
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          <td class="memname"><a class="el" href="struct_x_hdmiphy1___pll_param.html">XHdmiphy1_PllParam</a> XHdmiphy1_Channel::CpllParams</td>
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<p>Parameters for a CPLL. </p>

</div>
</div>
<a class="anchor" id="a4f48b4acc5459494a985eb01d5ab6a62"></a>
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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gaec55cf3dfcfa0c7cf9749c63690dd019">XHdmiphy1_PllRefClkSelType</a> XHdmiphy1_Channel::CpllRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the CPLL. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

</div>
</div>
<a class="anchor" id="ab40f4cd71a6a17e5fadfb0e51c96f310"></a>
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          <td class="memname">u64 XHdmiphy1_Channel::LineRateHz</td>
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<p><pre class="fragment">     The line rate for the
</pre><p> channel. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga71a574c5aedf401c9b7c59a173822f8f">XHdmiphy1_CfgLineRate()</a>, <a class="el" href="group__xhdmiphy1.html#ga31263f99c22623f852ea864fba080232">XHdmiphy1_GetLineRateHz()</a>, <a class="el" href="group__xhdmiphy1.html#gafa361514e8315c25876867a1ded2c99b">XHdmiphy1_HdmiCfgCalcMmcmParam()</a>, and <a class="el" href="group__xhdmiphy1.html#ga87f9523a81f1b648cfae0172bdd96f0b">XHdmiphy1_PllCalculator()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> XHdmiphy1_Channel::RxDataRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the RX datapath. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, and <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

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          <td class="memname">u8 XHdmiphy1_Channel::RxDataWidth</td>
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<p>In bits. </p>

<p>Referenced by <a class="el" href="xhdmiphy1__hdmi_8c.html#a026bd874ba52e36d8f0e770b962543f9">XHdmiphy1_HdmiQpllParam()</a>.</p>

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<p><pre class="fragment">     Bypasses the delay
</pre><p> alignment block for the RX output clock. </p>

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          <td class="memname">u8 XHdmiphy1_Channel::RxIntDataWidth</td>
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<p>In bytes. </p>

<p>Referenced by <a class="el" href="xhdmiphy1__hdmi_8c.html#a026bd874ba52e36d8f0e770b962543f9">XHdmiphy1_HdmiQpllParam()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga1b751875671500e5b0173be954368177">XHdmiphy1_OutClkSelType</a> XHdmiphy1_Channel::RxOutClkSel</td>
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<p>Multiplexer selection for which clock to use as the RX output clock. </p>

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          <td class="memname">u8 XHdmiphy1_Channel::RxOutDiv</td>
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<p><pre class="fragment">     Output clock divider D for
</pre><p> the RX datapath. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga4c7a948926fede8a6548c6cffe5fc830">XHdmiphy1_DruCalcCenterFreqHz()</a>, and <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a> XHdmiphy1_Channel::RxOutRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the RX output clock. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a> XHdmiphy1_Channel::RxProtocol</td>
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<p>The protocol which the RX path is used for. </p>

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<p>Current state of RX GT. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a0c603299dc1bafabcf0ecfe920bd412b">XHdmiphy1_HdmiGtRxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#a80cae1429b5d37ffec8de9763de00f56">XHdmiphy1_HdmiRxClkDetFreqChangeHandler()</a>, <a class="el" href="group__xhdmiphy1.html#ga5a0a82f90d7a0f1c4c8180cfb465de0a">XHdmiphy1_HdmiRxTimerTimeoutHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga4d998790546ec3dde5119376868686e6">XHdmiphy1_SysClkDataSelType</a> XHdmiphy1_Channel::TxDataRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the TX datapath. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, and <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

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          <td class="memname">u8 XHdmiphy1_Channel::TxDataWidth</td>
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<p>In bits. </p>

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<p><pre class="fragment">     Bypasses the delay
</pre><p> alignment block for the TX output clock. </p>

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          <td class="memname">u8 XHdmiphy1_Channel::TxIntDataWidth</td>
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<p>In bytes. </p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga1b751875671500e5b0173be954368177">XHdmiphy1_OutClkSelType</a> XHdmiphy1_Channel::TxOutClkSel</td>
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<p>Multiplexer selection for which clock to use as the TX output clock. </p>

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<a class="anchor" id="a6791024e367774619bbfeaedb022b6c1"></a>
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          <td class="memname">u8 XHdmiphy1_Channel::TxOutDiv</td>
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<p><pre class="fragment">     Output clock divider D for
</pre><p> the TX datapath. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga16dfea31e43d9da2c4c00cd0785b6248">XHdmiphy1_HdmiDebugInfo()</a>, and <a class="el" href="group__xhdmiphy1.html#gada0844e8a6a828bb7d512259aca11498">XHdmiphy1_HdmiTxTimerTimeoutHandler()</a>.</p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#gac87909fabb3f765c0be156e7082aea8e">XHdmiphy1_SysClkOutSelType</a> XHdmiphy1_Channel::TxOutRefClkSel</td>
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<p>Multiplexer selection for the reference clock of the TX output clock. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#ga0fa2836b8aac17e187bf1e01a462001a">XHdmiphy1_WriteCfgRefClkSelReg()</a>.</p>

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<a class="anchor" id="a878cc570db337b4cf90acb555fcec00f"></a>
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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga3f9002a6b4bc8e47f9c1fa68f8d0fb15">XHdmiphy1_ProtocolType</a> XHdmiphy1_Channel::TxProtocol</td>
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<p>The protocol which the TX path is used for. </p>

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          <td class="memname"><a class="el" href="group__xhdmiphy1.html#ga19e4c793abee3457123797eca4f61cd0">XHdmiphy1_GtState</a> XHdmiphy1_Channel::TxState</td>
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<p>Current state of TX GT. </p>

<p>Referenced by <a class="el" href="group__xhdmiphy1.html#gaa15dd35a9b1670aab091738d3ecca9df">XHdmiphy1_Hdmi_CfgInitialize()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#aa2c97194ee284139b2959025092cc122">XHdmiphy1_HdmiGtTxAlignDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#ad65db64a87467172db631b182c2ddd2d">XHdmiphy1_HdmiGtTxResetDoneLockHandler()</a>, <a class="el" href="xhdmiphy1__hdmi__intr_8c.html#afc3e2c76a28022e9d12a96990cc2fc83">XHdmiphy1_HdmiTxClkDetFreqChangeHandler()</a>, <a class="el" href="group__xhdmiphy1.html#gada0844e8a6a828bb7d512259aca11498">XHdmiphy1_HdmiTxTimerTimeoutHandler()</a>, and <a class="el" href="group__xhdmiphy1.html#ga1d8702f582054727e5bafc4e6cf32739">XHdmiphy1_HdmiUpdateClockSelection()</a>.</p>

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